//################################################################################
// MIT License
// Copyright (c) 2024 ZhangYihua
//
// Change Logs:
// Date           Author       Notes
// 2020-10-18     ZhangYihua   first version
//
// Description  : 
//################################################################################

`ifndef CPU_RW_AXI_SV_FILE
`define CPU_RW_AXI_SV_FILE

interface cpu_rw_axi_itf #(ADDR_BW=16, DATA_BW=32)
                          (input logic clk);
    logic [ADDR_BW-1:0] awaddr=0;
    logic awvalid=0;
    logic awready;

    logic [DATA_BW-1:0] wdata=0;
    logic wvalid=0;
    logic wready;

    logic [1:0] bresp;
    logic bvalid;
    logic bready=0;

    logic [ADDR_BW-1:0] araddr=0;
    logic arvalid=0;
    logic arready;

    logic [DATA_BW-1:0] rdata;
    logic [1:0] rresp;
    logic rvalid;
    logic rready=0;

    task cpu_wr_t;
        input integer gap;
        input logic [ADDR_BW-1:0] addr;
        input logic [DATA_BW-1:0] data;

        repeat(gap) begin
            @(posedge clk);
        end

        fork
            begin
                awaddr  <=`U_DLY addr;
                awvalid <=`U_DLY 1'b1;
                @(posedge clk);
                while(awready==1'b0) begin
                    @(posedge clk);
                end
                awvalid <=`U_DLY 1'b0;
            end

            begin
                wdata  <=`U_DLY data;
                wvalid <=`U_DLY 1'b1;
                @(posedge clk);
                while(wready==1'b0) begin
                    @(posedge clk);
                end
                wvalid <=`U_DLY 1'b0;
            end
        join

        bready <=`U_DLY 1'b1;
        @(posedge clk);
        while(bvalid==1'b0) begin
            @(posedge clk);
        end
        bready <=`U_DLY 1'b0;
    endtask

    task cpu_rd_t;
        input integer gap;
        input  logic [ADDR_BW-1:0] addr;
        output logic [DATA_BW-1:0] data;

        repeat(gap) begin
            @(posedge clk);
        end

        araddr  <=`U_DLY addr;
        arvalid <=`U_DLY 1'b1;
        @(posedge clk);
        while(arready==1'b0) begin
            @(posedge clk);
        end
        arvalid <=`U_DLY 1'b0;

        rready <=`U_DLY 1'b1;
        @(posedge clk);
        while(rvalid==1'b0) begin
            @(posedge clk);
        end
        data = rdata;
        rready <=`U_DLY 1'b0;
    endtask
endinterface

`endif
